Airline pilots rack up a lot of hours but get very little "stick time", and what they do get is extremely sedate flying to not scare the passengers / spill their drinks. Their primary skills are pushing buttons on the autopilot and talking in the radio and transcribing clearances.
A military pilot gets more effective stick time. But aerobatic pilots, ag pilots (but I repeat myself), and glider pilots gain a LOT more experience and skill per hour flown than an airline pilot.
I was working with the example given which was weak on two points, John Travolta gets paid and while his hours are impressive they nowhere near full time professional hours.
Military pilots are also professionals, and of the glider pilots how many of the best are trainers. Ag pilots are professionals, as are helicopter mustering pilots who are incredibly skilled. The majority of acrobatic pilots are also professional pilots. I’m not suggesting that great amateurs don’t exist just that a great amateur who has gone pro can often beat one that hasn’t.
I understand the sentiment, on one hand if I was rich I would be able to devote my time into constant improvement, but then maybe I wouldn’t have the same drive to succeed as having my livelihood dependent on the outcome. There is institutional knowledge gained by working in a research org that would be hard to replicate as an independent scientist.
I've been a gliding instructor, sometimes doing up to ten flights a day, all summer (e.g. when I was unemployed for a time). In the NZ/Aus/UK style clubs you don't get paid for it, but then it doesn't cost you anything either.
Layoffs just seem to be part of life in the US tech industry.
Qualcomm announced laying off 66 people in San Diego today. And hundreds more at Meta and Oracle. Qualcomm laid off 260 or so in San Diego a year and a half ago in September 2024.
I got laid off from SiFive in February 2020 (one of 80). My boss and my boss's boss (who was the one who called me in for the good news) were themselves gonzo three months later. It seemed to be a pivot away from doing so much general infrastructure software development in-house. Palmer had moved on to Google two months earlier (and Rivos/Meta since) ... had he seen the writing on the wall?
It didn't seem to be personal. The founders seemed to not know the details in advance, only the "professional" management.
They laid off 80 people in the same time frame that everyone else was hiring because the cost of capital had fallen to zero (and in some industries below zero with government subsidies.) I don't think that's just "life in the tech industry," that's people who don't know what they're doing.
When I interviewed with Yunsup in 2017, the vision he was spinning was "we're going to make it very easy for people to produce application specific ICs with a toolbox of accelerators and a core ISA." That's where the whole "Moore's Law Only Ends Once" phrase came from... They wanted SiFive to be the "go to" fabless design bureau for when you wanted more performance than what you could squeeze out of the flattening performance curve.
It turns out that was hard. Harder than anyone in San Mateo or Milpitas could anticipate.
> It turns out that was hard. Harder than anyone in San Mateo or Milpitas could anticipate.
Was that it?
My impression was that it turned out to be hard to find people who weren't already making high volume custom ASICs but wanted to (and already had the skills to know what they wanted). People who were already had an experienced team making custom chips just wanted to license a core.
And then the PolarFire SoC got you 90% of the way there (and Zynq ten years earlier of course) for $36 for a chip with a 667 MHz HiFive Unleashed plus 23k LEs if you valued rapid hardware iteration over a custom $1 FE-310 variant.
- RISC-V is heavily used in embedded applications everywhere, to the point that Arm has announced they're stopping developing the Cortex-M line and sticking with what they currently have
- at least in the case of China and Russia, they already have machines using ISAs they developed and own themselves with higher performance than currently-available RISC-V
- RISC-V is not a "CPU technology" (that is, CPU micro-architecture) or a chipmaking technology. It's just a language for writing recipes, and says nothing at all about the medium or technology used to record and distribute and follow those recipes.
- within the next 12-24 months, RISC-V chips designed and made in the West will match or exceed those designed in China as many top CPU designers joined or founded RISC-V companies around 2021/2 (and Intel's ex "Royal Core" team in 2024).
All RISC ISAs are basically the same thing as far as compiler optimisation is concerned, and there is 40 years of work into that already.
I can't see any reason why the father of Zen and the designer of the M1 can't make a core for the simpler RISC-V ISA with basically the same (or better) µarch than the M1.
I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary?
Is there a compiler?
How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA?
There are many reasons.
The main one is that no architecture exists that models such a complex ternary processor.
At most, there are "on paper" implementations of much less complex architectures; no one has addressed the problem at this level.
Having a complete architecture and its hardware implementation now allows us to start developing software on something other than an emulator.
> ----
I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary?
> -----
No, it's a processor that's available now, both the current hardware implementation (on FPGA) and the Verilog/VHDL description for implementation on other architectures (ASIC?), as well as the specifications made available under license.
>----
Is there a compiler?
>----
Hmm, but I mentioned it in the paper; currently, a working cross-assembler (obviously) and a high-level language based on Rust are being designed/built.
>----
How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA?
>----
This is an interesting question; the answer is: currently, no.
We intend to provide (soon) comparative tests of this type.
The "G" extension for everything you want to run shrink-wrapped binaries on a standard OS has been there since the May 7 2014 "User Level ISA, Version 2.0", which is before RISC-V started to be promoted outside of Berkeley e.g. at Hot Chips 26 in August 2014, and the first RISC-V workshop in January 2015 in Monterey.
The name "G" has morphed into now (along with the C extension) being called "RVA20", which led to "RVA22" and "RVA23", but the principle is unchanged.
"An integer base plus these four standard extensions (“IMAFD”) is given the abbreviation “G” and provides a general-purpose scalar instruction set. RV32G and RV64G are currently the default target of our compiler toolchains."
Airline pilots rack up a lot of hours but get very little "stick time", and what they do get is extremely sedate flying to not scare the passengers / spill their drinks. Their primary skills are pushing buttons on the autopilot and talking in the radio and transcribing clearances.
A military pilot gets more effective stick time. But aerobatic pilots, ag pilots (but I repeat myself), and glider pilots gain a LOT more experience and skill per hour flown than an airline pilot.
I mean, just look at this glider flying lesson:
https://www.youtube.com/watch?v=MJapUCeDeOI
reply