> But Intel can probably still reuse lots of their cache coherency logic for external CXL.mem device access.
Holy cow, you nailed it: Intel can't get Optane fabrication cost down fast enough, and everyone is moving to CXL anyway, which presents its own latency challenges that tend to hide Optane performance advantage.
I wonder if you could leverage Optane's bit-level addressability in a shared memory pool scenario.
Holy cow, you nailed it: Intel can't get Optane fabrication cost down fast enough, and everyone is moving to CXL anyway, which presents its own latency challenges that tend to hide Optane performance advantage.
I wonder if you could leverage Optane's bit-level addressability in a shared memory pool scenario.
Sorry to see this tech go...