Gate pitch is not the same as gate length. The smallest feature size is usually the transistor gate length. In Samsung 14nm processes for example the drawn fin length is in fact 14nm. The actual physical size of the fin is closer to 8nm but I believe the whole structure is still close to 14.
The "divergence" started happening long before finfets where Intel is concerned, but they weren't manufacturing for anyone else. For the rest of the foundries, it still followed somewhat logically, if not exactly, down to 14 at least.
The "divergence" started happening long before finfets where Intel is concerned, but they weren't manufacturing for anyone else. For the rest of the foundries, it still followed somewhat logically, if not exactly, down to 14 at least.